Virtualization of Programmable Forwarding Planes

Abstract: Effective and efficient provisioning of shared cloud computing infrastructures requires combining the best approaches to materialize virtual instances of servers, network functions, switches, controllers, etc. These approaches must also provide abstractions that are convenient for operating and managing virtual resources independently. In the context of virtualization of programmable data planes, in Software Defined Networks (SDN), existing approaches fail to offer effective abstractions of virtual programmable switches. Instead, they only support switch emulation through a general-purpose program and therefore offer no guarantees of isolation or performance. Based on the previous experience of the research proponent in programmable data planes, the objective of the project proposal is to conceive a virtualization architecture capable of partitioning the physical switch into a set of virtual switches that operate in parallel, for independent control by network operators. many different. The design proposal will be guided by two design principles, data plane slicing and control plane abstraction. In short, the goal is to ensure that the same code written for a physical switch can run on the virtual switch, without any modifications or specific compilation process. The project will focus on designing two virtualization architectures: full, when the hypervisor provides strong isolation between virtual instances, and lightweight, in which switches are virtualized in containers, using functions and libraries common to other virtual switches. For proof of concept, it is planned to prototype and run the virtualization environment on a Xilinx Virtex-7 690T NetFPGA-SUME Programmable Board (already available on INF-UFRGS) with 4x10G SFP+ ports, using Xilinx Vivado Design Suite, Xilinx SDNet 2018.2 and the P4 language for encoding virtual switches. Furthermore, it is planned to experiment with virtualization architectures on an LDA c5 Programmable Switch with 48×12.5G ZSFP+ ports, equipped with Xilinx VCU-128 FPGA (in process of being acquired by INF-UFRGS within the scope of another current research project). It is also planned to prospect contacts with national and international companies to assess the feasibility of prototyping a programmable switch that natively supports virtualization.

Ano Inicio: 2021

Ano Fim: 2024

Coordenador Local: Weverton Luis da Costa Cordeiro

Agência de Fomento: CNPq